1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which allows redundant substitution information (e.g., address information), information used for device adjustments and the like to be written separately in a nonvolatile memory cell. The present invention also relates to an electronic information apparatus using such a nonvolatile semiconductor memory device.
2. Description of the Related Art
A conventional nonvolatile semiconductor memory device has a redundant function of substituting a malfunctioned word line, a malfunctioned bit line and a malfunctioned memory cell with a spare redundant word line, a spare redundant bit line and a spare redundant memory cell, respectively, so as to improve a defect rate.
In general, when the malfunctioned word line, bit line or memory cell is detected in a semiconductor memory device by a tester during a production shipment test, the tester causes a redundant address memory circuit provided in the same semiconductor memory device to store address information of the malfunctioned word line, line or memory cell. This address information stored in the redundant address memory circuit is ref erred to as the xe2x80x9cmalfunctioned addressxe2x80x9d, xe2x80x9credundant addressxe2x80x9d or xe2x80x9cdefective addressxe2x80x9d.
In a DRAM, an SRAM or the like, a redundant address memory circuit including fuses made of polysilicon is generally used while the nonvolatile semiconductor memory device, which uses floating gate transistors as memory cells of a main memory circuit, uses similar floating gate transistors to those of the main memory circuit as the memory cells of the redundant address memory circuit (hereinafter, referred to as the xe2x80x9credundant memory circuitxe2x80x9d).
An operation principle of the conventional redundant memory circuit used in a nonvolatile semiconductor memory device is now described with respect to a case where a word line of the nonvolatile semiconductor memory device is defective. When the defective word line is substituted with the redundant word line, an address of the defective word line is stored in the redundant memory recruit
The redundant memory circuit is a memory circuit addressable according to contents (which is referred to as a xe2x80x9cCAM (Content-Addressable Memory)xe2x80x9d). When address information is input to the main memory circuit, this address information is always input to the redundant memory circuit (CAM) as well. When an address contained in the input information is identical to an address stored in the redundant memory circuit, the redundant memory circuit is validated so as to break the connection to the defective word line and switch over to the connection to the redundant word line.
In the main memory circuit having a capacity of about several mega bits, several defects can occur, and therefore the number of restorable defective word lines corresponds to the number of the redundant word lines provided in the main memory circuit. Each redundant word line is combined with a redundant memory circuit which stores address information for a corresponding defective word line. In order to correct for N defects, N redundant word lines and N redundant memory circuits are required. Further, the redundant memory circuit requires a single validation bit, which indicates that a redundant circuit corresponding to the redundant memory circuit can be actually operated when address information for the defective word line is input to the redundant memory circuit. Where word line address information for the main memory circuit has a size of M bits, the redundant memory circuit is required to include memory cells for at least M+1 bits of information. Accordingly, in order to satisfy these requirements, the total number of bits required by the redundant memory circuit is Nxc3x97(M+1).
FIG. 5 shows one possible way of configuring memory and readout cells for a defective address bit (or a validation bit), that is, one of the M+1 cell circuits of the redundant memory circuit, and its associated redundant information readout circuit, is shown.
In FIG. 5, drains of floating gate transistors TGF1 and TGF2 are respectively connected to both ends (points C or D) of a latch circuit via respective NMOS transistors T3 and T4, which are turned on during a reading operation. Sources of floating gate transistors TGF1 and TGF2 can be connected to ground (not shown). A source voltage VS applied to the floating gate transistors TGF1 and TGF2 is 0 V during reading or writing operations and is about 6 V during an erasing operation.
The NMOS transistors T3 and T4 also have a bias effect for reducing a drain voltage applied to the floating gate transistors TGF1 and TGF2 so as to prevent drain disturb caused to the floating gate transistors TGF1 and TGF2. These two floating gate transistors TGF1 and TGF2 have a common word line VGF.
Sources of NMOS transistors T9 and T10 of this latch circuit are connected to a drain of an NMOS transistor T8 which is turned off when the transistors TGF1 and TGF2 are in a reading operation. That is, during the reading operation, the latch circuit does not perform data-hold, and after the reading operation, i.e., after data has been validated, the latch circuit holds data. One end (point D) of the latch circuit is connected to a drain of an NMOS transistor T7 for initializing data in the latch circuit. A source of the NMOS transistor T7 is connected to ground.
NMOS transistors T5 and TI5 are connected in series between the drain of the floating gate transistor TGF1 and a VPRG input port to which a write voltage VPRG is applied when writing data to the floating gate transistor TGF1. The NMOS transistors T5 and TI5 are always in an OFF state unless a writing operation is performed. Similarly, NMOS transistors T6 and TI6 are connected in series between the drain of the floating gate transistor TGF2 and the VPRG input port.
When either one of the floating gate transistors TGF1 and TGF2 is programmed, an output Out of this cell circuit takes a logic level xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d according to a state of either one of the floating gate transistors TGF1 and TGF2. An operation principle of reading data from the redundant memory circuit CAM is now described with respect to a case where the floating gate transistors TGF1 and TGF2 are respectively in an erasing state and a writing state.
Unlike a writing operation, in the operation of reading redundant information, all the transistors T5, TI5, T6 and TI6 are in an xe2x80x9cOFFxe2x80x9d state. Further, a read signal VB is at a low level and the transistors T3 and T4 are in an xe2x80x9cOFFxe2x80x9d state. In this case, the floating gate transistor TGF1 is isolated from the PMOS transistor T1 and the NMOS transistor T9 of the latch circuit by the transistor T3, and the floating gate transistor TGF2 is isolated from the PMOS transistor T2 and the NMOS transistor T10 of the latch circuit by the transistor T4.
Further, an inverted signal NVB to the readout signal VB is at a high level and the NMOS transistor T8 is in an xe2x80x9cONxe2x80x9d state. Accordingly, the latch circuit is formed by the transistors T1, T2, T8, T9 and T10 so as to hold data.
Thereafter, when an initialization signal INT is at a high level, the transistor T7 is turned on so that a potential at point D (the drain side) of the transistor T7 is at a low level (a ground level). The output Out provided via inverters INV1 and INV2 by the redundant memory circuit CAM has a low level equal to the level of the potential at point D.
On the other hand, at another output side (i.e., point C) of the latch circuit formed by the transistors T1, T2, T8, T9 and T10, a voltage applied at point C is at a high level equal to the level of a power supply voltage Vcc since the transistor T1 is turned on by the low-level potential at point D. Thereafter, when the initialization signal INT is at a low level, the transistor T7 is turned off. Further, the readout signal VB is at a high level, and therefore the inverted signal NVB with respect to the read signal VB is at a low level. At this time, the sources of the transistors T9 and T10 are isolated from ground, so that the data-hold is broken. Simultaneously, the transistors T3 and T4 are turned on, and therefore two arms of a ratio arm circuit are formed between the power supply Vcc and a common input port of the floating gate transistors TGF1 and TGF2 to which the source voltage VS is applied (ground potential during a reading operation). One of the two arms includes transistors T1 and T3, and the floating gate transistors TGF1, which are connected in series. The other of the two arms includes transistors T2 and T4, and the floating gate transistor TGF2, which are connected in series.
In an initialization operation, when the potential at point D is at a low level, the transistor T1 is turned on, and the potential at the drain (point C) of the transistor T3, i.e., a gate voltage of the transistor T2, is at a high level, and thus the transistor T2 is turned off. In this case, the drain (point D) of the transistor T4, i.e., agate voltage of the transistor T2, is at a low level, and therefore the transistor T1 maintains an xe2x80x9cONxe2x80x9d state.
In the case where the floating gate transistor TGF1 is in an erasing operation, i.e., the floating gate transistor TGF1 is turned on, when the current driving power of the floating gate transistor TGF1 is sufficiently higher than that of the PMOS transistor T1, the potential at point C is at a low level. Simultaneously, a gate voltage of the PMOS transistor T2 is at a low level, and therefore the transistor T2 is turned on and point D is charged by the power source voltage Vcc so that the potential at point D reaches a high level.
The floating gate transistor TGF2 is in a writing operation, i.e., in an xe2x80x9cOFFxe2x80x9d state, the potential at point D maintains a high level, and therefore the transistor T1 is turned off.
Thereafter, the read signal VB and the inversion signal NVB with respect to the read signal VB are respectively at low and high levels, so that a latch circuit is formed by the transistors T1, T2, T8, T9 and T10 so as to hold data, and the output Out provided via inverters INV1 and INV2 by the cell circuit is at a high level. In this manner, a value for an address bit (or a validation bit) is determined by the output Out from the cell circuit.
When holding data in the floating gate transistors TGF using the latch circuit, a single-end circuit as shown in FIG. 6, different to the differential-type circuit shown in FIG. 5, is generally used for configuring the redundant memory circuit CAM which uses the floating gate transistors TGF and the redundant information readout circuit associated with the redundant memory circuit CAM.
The single-end circuit of FIG. 6 is different from the differential-type circuit of FIG. 5 in that the single-end circuit of FIG. 6 does not include the serially-connected floating gate transistor TGF2 and NMOS transistor T4 which is turned on when the floating gate transistor TGF2 is in a reading operation. Further, the single-end circuit of FIG. 6 does not include the transistor T8 which controls data-hold in the latch circuit, like the differential-type circuit of FIG. 5 does. Such a single-end circuit is disclosed in Japanese Patent Application No. 10-238711. Alternatively, a bistable multivibrator (Japanese Laid-Open Patent Publication No. 8-7595) as shown in FIG. 7, which also does not hold data in the latch circuit, can be used as the redundant information readout circuit.
In the case where the cell circuit corresponds to one of M defective address bits, outputs from M cell circuits, i.e., an output from the redundant information readout circuit, are input to one input port of an exclusive-OR gate. Corresponding address bits received by the main memory circuit are input to the other input port of the exclusive-OR gate. Outputs from the exclusive-OR gate each corresponding to a different address bit in the single redundant memory circuit are input to an input port of a NOR gate. The NOR gate outputs a logic level xe2x80x9c1xe2x80x9d only when all the input address bits match the corresponding address bits in the redundant memory circuit. The output from the NOR gate is validated by an output corresponding to a validation bit from a memory cell, e.g., from an AND gate. The output from the AND gate is the output from the redundant information readout circuit and is used to open a redundant path when an address input to the main memory circuit corresponds to a defective address stored in the redundant memory circuit.
In general, the defective address is written in the redundant memory circuit only during a test operation. When any defect is detected, a defective address is written in the redundant memory circuit. Each time any defect is detected, a defective address is written in a corresponding redundant memory circuit.
In this normal operation of the nonvolatile semiconductor memory device as described above, an address input to the nonvolatile semiconductor memory device is simultaneously input in the main memory circuit and the redundant memory circuit. As described above, when the input address corresponds to an address stored in the redundant memory circuit, a redundant path corresponding to the address is open. Accordingly, in order to input the defective address in the redundant memory circuit, each address bit of the nonvolatile semiconductor memory device is input to a corresponding cell of the redundant memory circuit. When a defect is detected at an address where the testing operation is being performed, a prescribed programming is executed according to instructions by a testing device.
FIG. 8 is a circuit diagram showing a primary structure of a conventional nonvolatile semiconductor memory device including a main memory circuit and a redundant memory circuit. For simplification of description, FIG. 8 only illustrates the floating gate transistors TGF, the transistors T5 and TI5, the gate voltage VGF and source voltages VS applied to the floating gate transistors TGF, the voltage VPRG, which is applied to a drain of the floating gate transistor TGF during a writing operation, and the redundant information readout circuit (a CAM readout circuit), which are shown in FIGS. 5 through 7, a memory cell array of the main memory circuit, and a row decoder for selecting a word line corresponding to a memory cell address.
In practice, the redundant memory circuit CAM and its associated redundant information readout circuit (a CAM readout circuit) include cell circuits corresponding to Nxc3x97(M+1) bits. Each of transistors T51, T52 and T53 has a similar function to that of the transistor denoted by T5 in FIGS. 5-7. Transistors TI51, TI52 and TI53 are respectively used to isolate the transistors T51, T52 and T53 from their corresponding floating gate transistor TGF in the redundant memory circuit CAM.
In FIG. 8, MVPRG0, MVPRG1 and MVPRG2 denote bit lines for memory cells M in the main memory circuit. MVS1, MVS2 and MVS3 denote source potential of the memory cells M in the main memory circuit. In this circuit structure, the row decoder for the main memory circuit is used to select a word line W so as to write redundant information (a defective address) in the memory cell (the floating gate transistor TGF) in the redundant memory circuit CAM.
Conventionally, in order to efficiently realize such a circuit structure, unnecessary spaces in the circuit are reduced by employing a circuit layout shown in FIG. 9.
FIG. 9 shows a circuit layout of a semiconductor chip including: the row decoder for selecting a word line W; a column decoder circuit for selecting a bit line B in a memory cell array, which corresponds to an address in the main memory circuit; the main cell array in the main memory circuit; and a sense amplifier for reading data from the main memory circuit. It should be noted that in FIG. 9, lines denoted by B and W do not represent actual word lines W and bit lines B themselves but only represent directions along which the word lines W and bit lines B are provided. A swapped signal shown in FIG. 9 is used to open a redundant path when a defective address to be substituted is input to the main memory circuit. The swap signal is output by the redundant memory circuit CAM so as to be input to the row decoder and column decoder.
By employing the circuit layout shown in FIG. 9, unnecessary spaces are not provided and a line from the redundant memory circuit CAM to each decoder can be short.
Next, a nonvolatile semiconductor device having a fast readout function, such as synchronous burst readout and page-mode readout, is considered. FIG. 10 shows an example of circuit layouts of the nonvolatile semiconductor device having a fast read function with the circuit structure shown in FIG. 8 being maintained.
The nonvolatile semiconductor memory device having a fast readout function requires a plurality of sense amplifiers. As shown in FIG. 10, in general, by changing the circuit structure shown in FIG. 9 such that respective directions of the bit lines B and word lines W for the main memory array are interchanged with each other, the sense amplifiers are positioned in a direction along which the bit lines B are provided so as to reduce an output load provided to the bit lines and sense amplifiers as much as possible. Along with this change, the row decoders and column decoders are rearranged from the arrangement shown in FIG. 9 to the arrangement shown in FIG. 10.
In FIG. 10, since the redundant memory circuit CAM is opposed to the row decoder with respect to the memory cells M, a signal output by the redundant memory circuit CAM is input to the row decoder detouring around the memory cells M, causing an extremely heavy line load. This adversely affects a speed of a signal transferred from the redundant memory circuit CAM to the row decoder. Therefore, when an address of a defective word line substituted with a redundant word line is input to the main memory circuit, there is a delay in reading the address as compared to the case of reading an address of a normal word line. Further, as shown in FIG. 10, a circuit layout area is increased because of unnecessary space existing in a region below the redundant memory circuit CAM in FIG. 10.
In the redundant memory circuit CAM, the redundant memory circuit cells corresponding to Nxc3x97(M+1) bits are arranged as shown in FIGS. 5-7. FIG. 11 shows part of the redundant memory circuit including the redundant memory circuit cells shown in FIG. 5. In FIG. 11, for simplification of description, the redundant memory circuits CAM corresponding to a three-bit output are shown.
The cell circuits are commonly provided with the signal VB which is at a high level when data is read from the floating gate transistor TGF, the inverted signal NVB to the floating gate transistor TGF, the word line voltage VGF, the bit line voltage VPRG which is a high voltage applied to the drain of the floating gate transistor TGF so as to write data in the memory cell (the floating gate transistor TGF) in the redundant memory circuit CAM, and the source voltage VS of the floating gate transistor TGF. On the other hand, selection signals PROG and NPROG used for selecting the floating gate transistor TGF to which data is written are provided to each redundant memory circuit cell.
Since the conventional redundant memory circuit CAM uses all the memory cells thereof, when there is a defect in a single memory cell in the redundant memory circuit CAM, an entire chip including the redundant memory circuit CAM results in a defective chip which cannot be relieved by the redundant memory circuit CAM. Further, when there is a defect in a bit line to which the bit line voltage VPRG for writing is applied, it is not possible to write data in all the memory cells in the redundant memory circuit CAM, whereby the entire chip including the redundant memory circuit CAM also results in a defective chip which cannot be relieved by the redundant memory circuit CAM.
Furthermore, since the memory cells in the redundant memory circuit CAM are designed according to the same design rule as the memory array in the main memory circuit, as the semiconductor memory device becomes more compact, a space between adjacent cells in the redundant memory circuit becomes narrower. This increases the possibility that circuit failure occurs due to a short-circuit between the adjacent cells.
Further still, in the conventional redundant memory circuit cells, there is a possibility that redundant information (a defective address) cannot be read from the floating gate transistor TGF in a normal manner when the power supply voltage is low (e.g., about 1.8 V). The principle of the aforementioned readout operation is described with reference to an example of the redundant memory circuit cell shown in FIG. 5.
An output of the redundant memory circuit cell is determined according to a programmed transistor of two transistors in the redundant memory circuit cell. Data representing a state (an output) of the cell is read from a drain of one of PMOS transistors (e.g., T2).
In this case, the floating gate transistor TGF1 is in a writing state, and the floating gate transistor TGF2 is in an erasing state. A voltage applied at point D (drain side) of the transistor T2 is at a low level since the floating gate transistor TGF2 is in an erasing state, i.e., in an xe2x80x9cONxe2x80x9d state. The voltage is input to a gate of the transistor T1 so that the transistor T1 is turned on. Further, a voltage applied at point C (drain side) of the transistor T1 is at a high level since the floating gate transistor TGF1 is in a writing state, i.e., in an xe2x80x9cOFFxe2x80x9d state. The voltage is input to the transistor T2 so that the transistor T2 is turned off and the voltage applied at point D of the transistor T2 maintains a low level.
However, when this conventional redundant memory circuit is used with a low power supply voltage, the driving power of the floating gate transistor TGF2 is lowered, and therefore the voltage applied at point D (drain side) of the transistor T2 is decreased to a midpoint potential but not to a low level.
In order to avoid this, it is necessary to reduce the power of the PMOS transistors T1 and T2 or an upper limit of the threshold voltage of the floating gate transistor TGF in an erasing state.
In the case where the power of the PMOS transistors T1 and T2 is reduced, provided that gate widths of the PMOS transistors T1 and T2 have been designed so as to be minimum under a design rule, gate lengths of the PMOS transistors T1 and T2 are required to be increased, resulting in an increase in a circuit layout area. On the other hand, in the case where the upper limit of threshold voltage of the floating gate transistor TGF in an erasing state is reduced, the time required for a testing operation becomes longer.
As described above, in the circuit arrangement of FIG. 10, where the sense amplifiers are disposed in the direction along which the bit lines B are provided, the nonvolatile semiconductor circuit can have a fast readout function while the redundant memory circuit CAM is opposed to the row decoder with respect to the memory cells M, and therefore a signal output from the redundant memory circuit CAM is input to the row decoder detouring around the memory cells M, causing an extremely heavy line load, so that a speed of a signal transferred from the redundant memory circuit CAM to the row decoder is adversary affected. Therefore, when an address of a defective word line substituted with a redundant word line is input to the main memory circuit, there is a delay in reading the address as compared to the case of reading an address of a normal word line. Further, as shown in FIG. 10, a circuit layout area is increased because of unnecessary space existing in a region below the redundant memory circuit CAM in FIG. 10.
According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a main memory circuit including memory cells arranged in a matrix form, the memory cells being formed of electrically writable and erasable floating gate transistors each provided at an intersection of a bit line and a word line: and a redundant substitution information memory circuit including a plurality of memory cells formed of the electrically writable and erasable floating gate transistors, in which one end of each memory cell formed of the floating gate transistors in the redundant substitution information memory circuit can be electrically connected to and disconnected from the bit line in the main memory circuit by a selection transistor so as to supply the memory cells in the redundant substitution information memory circuit with current for writing and reading operations via the bit lines.
In one embodiment of this invention, at least two pairs of the redundant memory circuits and redundant information readout circuits are used for storing identical redundant memory information, and a logic circuit for performing a logical operation on outputs from the two redundant information readout circuits is connected to an output of each of the two redundant information readout circuits so as to reflect a normal output from either of the two redundant memory circuits in an output provided as one-bit binary information from the logic circuit.
In one embodiment of this invention, a single selection transistor is connected to drains of the plurality of memory cells included in the redundant substitution information memory circuit so as to form a parallel circuit.
In one embodiment of this invention, the redundant substitution information memory circuit is capable of storing information used for adjusting the memory device in addition to redundant substitution information.
In one embodiment of this invention, the number of the memory cells used in the redundant substitution information memory circuit is smaller than the number of the bit lines in the main memory circuit, and at least either of unused redundant substitution information memory cells or dummy bit lines are provided at a regular interval.
According to another aspect of the present invention, there is provided an electronic information apparatus including the nonvolatile semiconductor memory device of claim 1 for processing information.
Hereinafter, effects of the above-described structures are described. By changing the arrangement of the floating transistors in the redundant substitution information memory circuit so as to be in a direction along which the bit lines are provided, rather than a direction along which the word lines are provided as in the conventional nonvolatile semiconductor memory device, it is possible to prevent an increase in load provided to the lines in the redundant memory circuit as shown in FIG. 10 so as to provide a fast reading speed and it is also possible to eliminate unnecessary spaces in the circuit layout as shown in FIG. 10. Further, as compared to the conventional nonvolatile memory device in which the redundant memory circuit is positioned in a direction along which the word lines are provided, it is possible to eliminate the bit lines exclusively used for the redundant memory circuit as well as the redundant memory circuit selection transistors and their associated lines, thereby reducing a circuit layout area, i.e., an area of the chip can be reduced.
Further, the respective memory cells of the redundant substitution information memory circuits of two pairs (or more) store identical one-bit binary information, and therefore even in the case where there is a defect in one pair of floating gate transistors among the floating gate transistors in the redundant substitution information memory circuits of two pairs, when the other pair of the floating gate transistors are normal, the output having a normal value can be provided from the redundant substitution information memory circuit, thereby further improving circuit redundancy.
Furthermore, by providing at least either of the unused redundant substitution information memory cells or the bit lines at a regular interval in the sequentially-provided redundant memory circuits and redundant information readout circuits, a short-circuit is prevented from occurring between the adjacent cell circuits, thereby improving fault tolerance. This increases the possibility that the defective bit line B is relieved.
Further still, in one of the two arms formed between the redundant memory circuit and the redundant information readout circuit, a drain voltage of a PMOS transistor is determined by current power of the PMOS transistor and the two floating gate transistors. Therefore, in the case where the current driving power of the floating gate transistors is lower than that of the PMOS transistor, it is particularly effective that the drain voltage of the PMOS transistor is low.
Further still, the parallel circuit formed by the plurality of floating gate transistors realizes the redundant memory circuit which can perform reliable reading operation even at a low voltage.
Thus, the invention described herein makes possible the advantages of providing a nonvolatile semiconductor memory device in which high readout speed is realized by reducing load provided to lines in a redundant memory circuit and a circuit layout area, i.e., an area of a chip, is reduced by eliminating unnecessary spaces in the circuit layout.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.